PRBS Generator using VHDL

Abstract

Pseudo random binary sequence is essentially a random sequence of binary numbers. So PRBS generator is nothing but random binary number generator.  It is ‘random’ in a sense that the value of an element of the sequence is independent of the values of any of the other elements. It is 'pseudo' because it is deterministic and after N elements it starts to repeat itself, unlike real random sequences. The  implementation  of  PRBS  generator  is  based  on  the  linear  feedback  shift  register (LFSR). The PRBS generator produces a predefined sequence of 1's and 0's, with 1 and 0 occurring with the same probability. A sequence of consecutive n*(2^n -1) bits comprise one data pattern, and this pattern will repeat itself over time. In  this  project,  the  entire  design  of  the  PRBS  generator  was  implemented  using  VHDL programming language and the simulation were done and tested on the XILINX ISE 9.1i simulator


  VHDL Code for D Flip Flop



library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 


---- Uncomment the following library declaration if instantiating 
--library UNISIM; 
--use UNISIM.VComponents.all; 


entity dff is 
    Port ( CLK : in std_logic; 
           RSTn : in std_logic; 
           D : in std_logic; 
           Q : out std_logic); 
end dff; 


architecture Behavioral of dff is 
begin 
  process(CLK) 
  begin 
    if CLK'event and CLK='1' then 
      if RSTn='1' then 
        Q <= '1'; 
      else 
        Q <= D; 
      end if; 
    end if; 
  end process; 
end Behavioral; 


  
VHDL CODE FOR PRBS 


library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 


---- Uncomment the following library declaration if instantiating 
--library UNISIM; 
--use UNISIM.VComponents.all; 


entity lfsr is 
    Port ( CLK : in std_logic; 
           RSTn : in std_logic; 
           data_out : out std_logic_vector(15 downto 0)); 
end lfsr; 


architecture Behavioral of lfsr is 


component dff 
Port ( CLK : in std_logic; 
           RSTn : in std_logic; 
           D : in std_logic; 
           Q : out std_logic); 
end component; 
signal data_reg : std_logic_vector(15 downto 0); 
signal tap_data : std_logic; 


begin 
  process(CLK) 
  begin 
    tap_data <= (data_reg(1) xor data_reg(2)) xor (data_reg(4) xor 
data_reg(15)); 
  end process; 


  stage0: dff 
    port map(CLK, RSTn, tap_data, data_reg(0)); 


g0:for i in 0 to 14 generate 


    stageN: dff 
      port map(CLK, RSTn, data_reg(i), data_reg(i+1)); 


  end generate; 


  data_out <= data_reg after 3 ns; 
end Behavioral;