Power optimization of Linear Feedback Shift
Register (LFSR) for Low Power BIST
This
paper proposes a low power Linear Feedback Shift Register (LFSR) for
Test Pattern Generation (TPG) technique with reducing power dissipation
during testing. The correlations between the consecutive patterns are
higher during normal mode during testing. The proposed approach uses the
concept of reducing the transitions in the test pattern generated by
conventional LFSR. The transition is reduced by increasing the
correlation between the successive bits. The simulation result show that
the interrupt controller benchmark circuit's testing power is reduced
by 46% with respect to the power consumed during the testing carried by
conventional LFSR.
BIST ARCHITECTURE
It
is very important to choose the proper LFSR architecture consumes
different power even for same polynomial. Another .Problem associated
with choosing LFSR is LFSR design issue, which includes LFSR
partitioning, in this the LFSR are differentiated on the basis of the
basis of hardware cost and testing time cost.
A
typical BIST architecture consists of a test pattern generator (TPG),
usually implemented as a linear feedback shift register (LFSR), a test
response analyzer (TRA), implemented as a multiple input shift register
(MISR), and a BIST control unit (BCU), all implemented on the chip
(Figure 1). This approach allows applying at-speed tests and eliminates
the need for an external tester. The BIST architecture components are
given below
Circuit under Test (CUT):
It is the portion of the circuit tested in BIST mode. It can be
sequential, combinational or a memory. Their Primary Input (PI) and
Primary output (PO) delimit it.
- Test pattern Generator(TPG): It generates the test patterns for CUT. It is a dedicated circuit or a microprocessor. The patterns may be generated in pseudo random or deterministically.
- Multiple input signatures registers (MISR): it is designed for signature analysis, which is a technique for data compression. MISR efficiently map different input streams to different signatures with every small probability of alias. MISR are frequently implemented in built-in-self-test (BIST) designs, in which output responses are compressed by MISR
- Test
Response Analysis (TRA): It analyses the value sequence on PO and
compares it with the expected output BIST Controller Unit (BCU): It
controls the test execution; it manages the TPG, TRA and reconfigures
the CUT and the multiplexer. It is activated by the Normal/Test signal
- ALGORITHM FOR LOW POWER LFSRAs discussed in the previous section LFSR is used to generate test patterns for BIST. In this, test patterns are generated externally by LFSR, which is inexpensive and high speed LFSR is a circuit consists of flip-flops in series. LFSR is shift register where output bit is an XOR function of input bits. The initial value of LFSR is called seed value. LFSR's seed value has a significant effect on energy consumption. [3]. The output that influence the input are Called tap. A LFSR is represented by as polynomial, which is also known as characteristic polynomial used to determine the feedback taps, which determine the length of random pattern generation. The output of LFSR is combination of I's and O's. A common clock signal is applied to all flip-flops, which enable the propagation of logical values from input to output of flip-flops. Increasing the correlation between bits reduces the power dissipation. This can be achieved by adding more number of test vectors, which decreases the switching activity. LFSR is characterized by the polynomial by its characteristics polynomial and inverse of characteristics polynomial is generated polynomial.
